Semiconductor Process Engineer Resume Example
Wafer layout: a die-grid wafer disc beside the name, yield and node stats and a fab-tools table for semiconductor process, yield and equipment engineers.
Use this example Template: Semiconductor Process Engineer
Lin Yu-Ting
Summary
Process integration engineer with 8 years in 300 mm logic fabs, from 16 nm FinFET to 3 nm and gate-all-around development. I own module interactions across lithography, etch, deposition and CMP, drive yield learning with inline defect and electrical test data, run DOEs and split lots and transfer processes from R&D to high-volume manufacturing. I work closely with equipment vendors and customer product engineers to hit ramp targets.
Experience
- Own contact and middle-of-line integration for a 3 nm node during ramp; led the team that lifted defect-density yield by 6.5 points in two quarters
- Ran 40+ DOEs and split lots with etch and CMP modules; cut contact-resistance variation by 35%
- Built Python/JMP dashboards linking inline defects to wafer-sort bin maps, now used by 60 engineers
- Owned 14 dry-etch chambers for 28 nm and 14 nm lines; raised tool availability from 88% to 95% with chamber-match SPC
- Led 8D investigations with Lam Research on particle excursions
Fab tools & modules
| Module | Tools |
|---|---|
| Etch | Lam Kiyo, TEL Tactras |
| Deposition | AMAT Endura, ASM Pulsar |
| CMP | AMAT Reflexion |
| Metrology | KLA 39xx, Hitachi CD-SEM |
Summary example
Process integration engineer with [N] years in [N] mm logic fabs, from [N] nm FinFET to [N] nm and gate-all-around development. I own module interactions across lithography, etch, deposition and CMP, drive yield learning with inline defect and electrical test data, run DOEs and split lots and transfer processes from R&D to high-volume manufacturing. I work closely with equipment vendors and customer product engineers to hit ramp targets.
Example bullet points for a Semiconductor Process Engineer
- Own contact and middle-of-line integration for a [N] nm node during ramp; led the team that lifted defect-density yield by [N] points in two quarters
- Ran [N]+ DOEs and split lots with etch and CMP modules; cut contact-resistance variation by [X%]
- Built Python/JMP dashboards linking inline defects to wafer-sort bin maps, now used by [N] engineers
- Owned [N] dry-etch chambers for [N] nm and [N] nm lines; raised tool availability from [X%] to [X%] with chamber-match SPC
- Led [N]D investigations with Lam Research on particle excursions
Replace the [brackets] with your own numbers and facts. Never claim results you didn't achieve.
Skills to include
- FinFET / GAA
- Etch, CVD, ALD, CMP
- Yield & defect analysis
- DOE / SPC / 8D
- JMP
- Python
- KLA Klarity
- PDF Exensio
- SQL
Tips for a Semiconductor Process Engineer resume
- Put the hard requirements recruiters screen for in the top third: FinFET / GAA, Etch, CVD, ALD, CMP, Yield & defect analysis.
- List current credentials with the issuing body, e.g. Six Sigma Black Belt, Advanced Semiconductor Manufacturing (online).
- Give every recent role at least one measured result — for example d0 yield gain.
- Match the job title in your headline to the posting where it is honest to do so.
- Run the built-in resume checker and paste the job description into the keyword match before you download.
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